Data transmitted across a high speed system, such as between two chips on a highly integrated system or between circuits within a single chip, are typically sent without an accompanying clock signal. Due to limited bandwidth and other reasons, the data are frequently distorted during the transmission. Therefore, although the use of the clockless data reduces the complexity, power consumption and cost on sending side, it requires the receiving side to generate a clock signal to recover the distorted data. A clock data recovery (CDR) device that stably creates signal in synchronization with the received data is therefore important to ensure the quality of high speed data communication.